1. Field of the Invention
The present invention relates generally to methods for forming patterned layers within microelectronics fabrications. More particularly, the present invention relates to fluorine containing plasma etch methods for forming residue free patterned fluorine containing plasma etched layers within microelectronics fabrications.
2. Description of the Related Art
In the process of forming patterned fluorine containing plasma etched layers from corresponding blanket fluorine containing plasma etchable layers within microelectronics fabrications, it is common in the art of microelectronics fabrication to employ: (1) a patterned photoresist etch mask layer to define the patterned fluorine containing plasma etched layer desired to be formed; and (2) a fluorine containing plasma etch method which employs a fluorine containing etchant gas composition employing a fluorine containing etchant gas such as carbon tetrafluoride, trifluoromethane, hexafluoroethane and/or sulfur hexafluoride. Particularly common patterned fluorine containing plasma etched layers which are formed within microelectronics fabrications from corresponding blanket fluorine containing plasma etchable layers within those microelectronics fabrications include patterned fluorine containing plasma etched dielectric layers such as patterned silicon oxide dielectric layers, patterned silicon nitride dielectric layers and patterned silicon oxynitride dielectric layers.
While it is thus common in the art of microelectronics fabrication to form patterned silicon oxide dielectric layers, patterned silicon nitride dielectric layers and patterned silicon oxynitride dielectric layers through fluorine containing plasma etch methods employing patterned photoresist etch mask layers, such patterned dielectric layers are not formed entirely without problems within microelectronics fabrications. In particular, it is known in the art of microelectronics fabrication that when forming patterned fluorine containing plasma etched dielectric layers, such as patterned silicon oxide dielectric layers, patterned silicon nitride dielectric layers and patterned silicon oxynitride dielectric layers, there is commonly formed upon exposed surfaces of those fluorine containing plasma etched dielectric layers fluoropolymer residue layers which are not readily removable within oxygen plasma stripping methods typically employed in stripping from those fluorine containing plasma etched dielectric layers the photoresist etch mask layers employed in defining those fluorine containing plasma etched dielectric layers. Such fluoropolymer residue layers generally incorporate carbon derived from slight etching of photoresist etch mask layers and/or carbon derived from fluorocarbon fluorine containing etchant gases. Such fluoropolymer residue layers are typically subsequently removed from patterned fluorine containing plasma etched dielectric layers through wet chemical stripping methods which unfortunately often contribute to delamination of the fluorine containing plasma etched dielectric layers from the microelectronics fabrications within which they are formed.
A series of schematic cross-sectional diagrams illustrating the results of progressive stages in forming a microelectronics fabrication having formed therein such a fluorine containing plasma etched delaminated dielectric layer is shown within FIG. 1 to FIG. 4. Shown in FIG. 1 is a schematic cross-sectional diagram of the microelectronics fabrication at an early stage in its formation. Shown in FIG. 1 is a substrate 10 having formed thereover a series of patterned conductor layers 14a, 14b and 14c, where the series of patterned conductor layers 14a, 14b and 14c is sandwiched between a first dielectric layer 12 formed upon the substrate 10 and a second dielectric layer 16 formed over the substrate 10. The second dielectric layer 16 has a void 17 (with a seam integral thereto) formed therein interposed between the pair of patterned conductor layers 14b and 14c, such as is commonly encountered when forming dielectric layers, such as the second dielectric layer 16, conformally upon closely spaced microelectronics structures, such as the closely spaced pair of patterned conductor layers 14b and 14c. There is also shown in FIG. 1 formed upon the second dielectric layer 16 a pair of patterned photoresist layers 18a and 18b which expose a portion of the second dielectric layer 16 through which is desired to form a via accessing the patterned conductor layer 14a.
Shown in FIG. 2 is the results of etching through a fluorine containing etching plasma 20 the via through the second dielectric layer 16, thus forming the pair of patterned second dielectric layers 16a and 16b, while simultaneously reaching the patterned conductor layer 14a. As is common in the art of microelectronics fabrication, the fluorine containing etching plasma 20 typically employs an etchant gas composition comprising a fluorine containing etchant gas such as, but not limited to, carbon tetrafluoride, trifluoromethane, hexafluoroethane and/or sulfur hexafluoride. There is also shown in FIG. 2 a pair of fluoropolymer residue layers 22a and 22b formed upon the exposed portions of the patterned second dielectric layers 16a and 16b within the via.
Referring now to FIG. 3, there is shown a schematic cross-sectional diagram illustrating the results of further processing of the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2. Shown in FIG. 3 is the results of stripping through an oxygen containing stripping plasma 24 the patterned photoresist layers 18a and 18b from the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2. As is illustrated in FIG. 3, the fluoropolymer residue layers 22a and 22b are typically impervious to the oxygen containing stripping plasma 24 and thus remain upon the via sidewalls defined by the patterned second dielectric layers 16a and 16b. In order to remove the fluoropolymer residue layers 22a and 22b from the corresponding patterned second dielectric layers 16a and 16b it is typically necessary to employ a strong wet chemical stripping solvent such as but not limited to a monoethanolamine wet chemical stripping solvent.
The results of stripping the fluoropolymer residue layers 22a and 22b from the nucroelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 3 is shown by the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 4. As is illustrated in FIG. 4, although the fluoropolymer residue layers 22a and 22b have been stripped from microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 4, the wet chemical stripping solvent, such as the monoethanolamine wet chemical stripping solvent, intrudes into the void 17 through the seam integral thereto and upon thermal treatment of the resulting microelectronics fabrication there is formed from the void 17 a bubble 19 while simultaneously forming from the patterned second dielectric layer 16b a partially delaminated patterned second dielectric layer 16b'.
In light of the foregoing description, it is thus desirable within the art of microelectronics fabrication to develop methods and materials through which there may efficiently, economically and without delamination due to bubbles be formed residue free patterned fluorine containing plasma etched layers within microelectronics fabrications through fluorine containing plasma etching of corresponding blanket fluorine containing plasma etchable layers within those microelectronics fabrications. It is toward that goal that the present invention is generally directed.
Various methods have been disclosed in the art of microelectronics fabrication for forming residue free patterned layers within microelectronics fabrications.
For example, Wootton et al., in U.S. Pat. No. 5,496,438, discloses a method for removing a patterned photoresist etch mask layer from a patterned metal layer within an integrated circuit microelectronics fabrication in a fashion such that there is avoided corrosion induced staining of the patterned metal layer. The method employs an ashing of the patterned photoresist layer for a sufficiently long time period and at a sufficiently high temperature such that all residual corrosive gas absorbed within the patterned photoresist layer is exhausted while still maintaining thermal conditions below which the patterned metal layer begins to flow.
In addition, Langan et al., in U.S. Pat. No. 5,413,670, discloses a method for plasma etching fluorine containing plasma etchable layers from semiconductor substrate surfaces and semiconductor substrate processing reactor surfaces when fabricating integrated circuit microelectronics fabrications. The method employs a nitrogen trifluoride etchant gas in conjunction with an electropositive diluent gas at a concentration, pressure, flowrate and power optimized to obtain an optimally high etchrate of the fluorine containing plasma etchable layer while simultaneously miniming nitrogen trifluoride consumption. Through the method there is thus obtained an optimally efficient nitrogen trifluoride fluorine containing plasma etch method at a minimum operating cost.
Finally, Nguyen et al., in U.S. Pat. No. 5,597,983, discloses a method for removing a via sidewall polymer residue formed incident to anisotropic etching of a via through a conformal dielectric layer to reach a conductor layer within a microelectronics fabrication. The method employs a tetra methyl ammonium hydroxide (TMAH) photoresist developer to remove the via sidewall polymer residue without etching the conductor layer.
It is thus desirable within the art of microelectronics fabrication to develop methods and materials through which there may efficiently, economically and without delamination due to bubbles be formed residue free patterned fluorine containing plasma etched layers from corresponding blanket fluorine containing plasma etchable layers within microelectronics fabrications. More particularly desirable are methods and materials through which there may efficiently, economically and without delamination due to bubbles be formed residue free patterned fluorine containing plasma etched dielectric layers from corresponding blanket fluorine containing plasma etchable dielectric layers within integrated circuit microelectronics fabrications. It is toward these goals that the present invention is more specifically directed.